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Initially, both measurement and simulation results indicated deterministic fluctuations of the DARTS clock frequency, which depend strongly on the delay parameters, but could not be explained by noise or dynamic parameter variations.
By means of non-linear control theory we develop an explanation of these effects, and establish that any non-trivial closed-loop asynchronous circuit exhibits such deterministic timing variations.
This leads to Chip Multiprocessors where not all cores operate at maximum frequency.
Given that PV is non-deterministic at design-time, our mechanisms allow the fast and slow issue-queue entries to co-exist in turn enabling in-struction dispatch, issue and forwarding to proceed with mini-mal stalls.
Citation Context ...ation leadsto processors reaching different maximum frequencies for a given operating voltage, although CMPs are moretolerant of that variation .
Researchers have looked at fixing variation issues =-=-=-, ; one way is to com-pensate for this variation by increasing operating voltage. Abstract—Among the most pressing issues in current deep submicron VLSI circuits are large parameter variations, primarily caused by process technology imperfections, that result in excessive delay variations, and continuously increasing soft error rates.
In this paper, we present first results of the parameter sensitivity analysis of our DARTS fault-tolerant clock generation scheme.
Unlike conventional clocking techniques for GALS systems, DARTS does not use quartz oscillators, but generates approximately synchronized clocks by means of an asynchronous distributed algorithm.
This scheme is able to recover most of the performance loss when up to 5 % of the line-predictor entries are faulty and when no faults exist it does not degrade performance. This leads to Chip Multiprocessors where not all cores operate at maximum frequency.